Measuring ADC performance

Overview:

In this project, I evaluated the ATmega328P’s ADC by measuring offset and gain errors across different prescaler settings. To ensure reliable testing, I designed a Finite State Machine (FSM) that automated sampling and data transfer, improving repeatability. The results quantified how ADC clock prescaler configurations impact accuracy, providing valuable insights for real-time embedded designs where both temporal and behavioral precision are critical.

Preview:

Technical implementation:

Software Architecture:

Bare metal programming in C of a dual-state finite state machine:

State 1: Sampling ADC data
State 2: Stop sampling, ready to transfer data to Serial monitor

System Configuration:

Description:

MCU: ATmega328P (Arduino Uno R3)

Voltage Reference: 2.5V via voltage divider

Input Waveform: Sawtooth (0–2.5 V, 0.2 Hz, 1.25 V offset) — used as ADC test signal

FSM States:

S1: Sampling active, LED blinks at 1Hz
S2: Sampling off, LED blinks at 2Hz

Push Buttons: Manual FSM control via INT0/INT1

Timers & Interrupts:

Timer2: ~5ms sampling interval
Timer1: LED blink rate control
Timer0: 200ms software debounce
External Interrupts: Trigger FSM transitions

ADC Settings:

8-bit, left-aligned output
Single-conversion mode
Prescalers tested: 2 → 128

Sampling Strategy:

Samples stored in a fixed-size ring buffer (1500 entries)
ISR-driven logging via Timer2 for consistent timing

ADC Output (sampled):

The ADC output graphs show the performance of the ATmega328P’s ADC under different clock prescaler settings. The offset error stabilizes around -1.3 LSB as the prescaler increases, while the gain error shows a linear increase with higher prescaler values. This indicates a trade-off between sampling speed and accuracy, where lower prescaler settings yield faster sampling but higher offset errors, and higher settings provide more accurate results at the cost of slower sampling rates.

Insights:

ADC clock prescaler settings significantly impact accuracy
Lower prescaler values yield faster sampling but higher offset errors
Higher prescaler values improve accuracy at the cost of slower sampling rates
Finite State Machine (FSM) design ensures reliable and repeatable testing